3T Gain Cell Embedded DRAM Research Paper & Simulation (VLSI)

Researchers are always coming up with new ways to make computing systems faster, smarter, and more efficient. For this project I investigated a method for improving integrated circuits described in the paper “A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches”. These innovative new embedded DRAM configurations are just a few examples of how creativity and intellect coalesce to drive technological advance. My paper serves as an analysis and reflection of the proposed designs and solutions.

The design to the left was simulated using Cadence Virtuoso software. The purpose of the simulation is to test the different circuits described.

Using Cadence, the boosted 3T gain cell is simulated alongside the traditional 3T cell, as seen in the figure to the right. As seen in the results in Figure 13, the gain cell (green) is able to retain a low voltage for slightly longer than the traditional cell (red).